clk: sunxi-ng: h6: Reparent CPUX during PLL CPUX rate change
authorJernej Skrabec <jernej.skrabec@gmail.com>
Fri, 13 Oct 2023 18:17:12 +0000 (20:17 +0200)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Fri, 17 May 2024 09:50:51 +0000 (11:50 +0200)
commitf1fa9a9816204ac4b118b2e613d3a7c981355019
tree25e133b48e21cea19cb7c9c788ab033ea47884ea
parent83ac89e3797dfb0e43553847c55329a526a4bc7c
clk: sunxi-ng: h6: Reparent CPUX during PLL CPUX rate change

[ Upstream commit 7e91ed763dc07437777bd012af7a2bd4493731ff ]

While PLL CPUX clock rate change when CPU is running from it works in
vast majority of cases, now and then it causes instability. This leads
to system crashes and other undefined behaviour. After a lot of testing
(30+ hours) while also doing a lot of frequency switches, we can't
observe any instability issues anymore when doing reparenting to stable
clock like 24 MHz oscillator.

Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
Reported-by: Chad Wagner <wagnerch42@gmail.com>
Link: https://forum.libreelec.tv/thread/27295-orange-pi-3-lts-freezes/
Tested-by: Chad Wagner <wagnerch42@gmail.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Link: https://lore.kernel.org/r/20231013181712.2128037-1-jernej.skrabec@gmail.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/clk/sunxi-ng/ccu-sun50i-h6.c